AI Capex Is a Semiconductor Procurement Problem. Now It Has a Price Tag.

The Number That Changes the Frame

Stop modeling AI infrastructure as a software cycle with a hardware tail. It is a semiconductor procurement cycle with a software layer on top. The Semiconductor Industry Association and Deloitte made that case with hard numbers on June 1, publishing a virtual teardown of a state-of-the-art AI server rack that should sit in every CTO and CFO briefing deck going into H2 planning.

The headline: the report projects annual revenue for semiconductors used in AI data centers could reach $1.2 trillion by 2028, a nearly tenfold increase over the last four years, surpassing total global semiconductor sales from 2025 across all end uses by more than 50%. Read that twice. A single application vertical is projected to generate more chip revenue by 2028 than the entire global semiconductor industry did from every market combined in 2025.

The operational finding cuts deeper: chips account for more than 95% of a leading AI server rack's content value and more than 50% of the total capital expenditures required for building and operating an AI data center. When you buy an AI rack, you are almost entirely buying silicon. Real estate, cooling, power distribution, networking cables—they are rounding errors on the bill of materials.

What Is Actually Inside the Rack

The SIA-Deloitte methodology matters. The report, titled "Powering AI: The Semiconductor Ecosystem at the Foundation of Data Centers," conducts a virtual teardown of a state-of-the-art AI data server rack, the foundational unit of centralized AI infrastructure. That teardown produced component-level accounting most operator budgets obscure.

A single rack contains more than 4,500 packaged chips and approximately 20,000 semiconductor dies. The chip types span the full stack: AI accelerators, ASICs, FPGAs, CPUs, DPUs, networking chips, high-bandwidth memory, DRAM, SRAM, NAND flash memory, power management devices, controllers, sensors, and transceivers.

Value concentration is steep. AI accelerators account for the largest share of server rack value at 74%, with logic chips making up 70% of the semiconductor content within that category. But non-accelerator components are not noise. Power management, memory controllers, networking silicon, and analog devices are collectively necessary for the accelerator to function. Every layer has a supply chain.

The Supply Constraint Is Already Structural

The $1.2 trillion projection is a demand forecast. Whether supply can meet it is the actual question, and current evidence suggests it cannot—at least not without friction.

Advanced packaging is the tightest constraint. CoWoS (Chip-on-Wafer-on-Substrate) is the process TSMC uses to mount AI accelerators alongside high-bandwidth memory. Without it, chips cannot ship as usable products regardless of wafer availability. TSMC is scaling CoWoS capacity from approximately 35,000 wafers per month in late 2024 to a projected 130,000 wafers per month by the close of 2026. That is meaningful, but concentrated. Nvidia's decision to lock down more than half of TSMC's advanced packaging capacity through 2027 creates a challenging environment for other fabless chip designers.

All six fully booked TSMC facilities as of Q1 2026 are TSMC — three 2nm frontend fabs and three CoWoS advanced-packaging lines — with lead times stretching to 78–104 weeks. The bottleneck has shifted from wafer starts alone to a three-way constraint: advanced logic (2nm/3nm), CoWoS packaging, and HBM3E memory.

HBM supply is the second constraint. High-bandwidth memory has moved from a niche component to core AI infrastructure, with sales expected to grow from $15.2 billion in 2024 to $32.6 billion by 2026. HBM still costs about five times more than standard server DRAM, and supply depends on advances in packaging. Operators buying AI infrastructure compete for allocation of a scarce, expensive memory format whose supply runs through a handful of fabs at SK Hynix, Micron, and Samsung.

What the $4 Trillion Capex Figure Actually Means

To meet global demand for new AI applications, government and industry will invest over $4 trillion in new data center infrastructure through 2028, of which up to $2.8 trillion will be spent on semiconductors. The ratio matters: $2.8T of $4T total is chips. Concrete, power, cooling, land, and labor compete for the remaining $1.2T.

This reshapes how operators should evaluate AI infrastructure ROI. The cost floor is set by semiconductor pricing, fab yields, and packaging throughput—none negotiable at the rack level. A hyperscaler can negotiate power contracts and construction costs. It cannot negotiate the spot price of CoWoS capacity when Nvidia holds 60–70% of it.

For boards benchmarking AI capex against cloud migration cycles: that earlier cycle was primarily a software and services procurement event with commodity hardware underneath. This is inverted. Hardware is exotic, concentrated, and geopolitically exposed. Software is, relatively speaking, the commodity.

The $1.2 trillion projection likely assumes continued enterprise conversion from AI experimentation to production workloads. If that conversion slows—due to ROI uncertainty, regulatory friction, or efficiency gains reducing inference compute—the demand curve bends down. But even a significantly lower outcome, say 60–70% of the projected figure, would represent a structural transformation of the semiconductor industry.

What to Watch

1. CoWoS capacity utilization signals: CoWoS and SoIC utilization rates at TSMC are the binding constraint for flagship AI accelerators; any slowdown in packaging expansion will show up in shipment guidance before it appears in chip revenue. Listen to Nvidia, AMD, Broadcom, and Marvell earnings calls for allocation language.

2. HBM pricing trajectory: Budget for rising HBM and DRAM pricing in 2026, with high-teens to 20% increases. Samsung and SK Hynix have already signaled contract repricing. This is direct input cost for any operator deploying AI infrastructure at scale.

3. Hyperscaler chip partnership announcements: The 95% silicon content finding changes negotiating posture. Watch whether Microsoft, Google, Amazon, and Meta accelerate custom silicon programs (TPUs, Trainium, Maia, MTIA) to escape commodity chip pricing—or lock in long-term supply agreements with foundries to secure allocation ahead of the 2027–2028 demand peak.

4. Export control evolution: The report lands as U.S. policymakers debate how to preserve AI leadership through chip policy, export programs, manufacturing incentives, and access to global markets. Any tightening or loosening of export controls on advanced AI chips directly reshapes the $1.2T demand geography.

5. The 95% ratio itself: Monitor whether silicon content share holds as rack architectures evolve. Custom silicon, analog chiplets, and power management complexity could shift the ratio. If non-accelerator semiconductor content grows as a share, memory and analog suppliers become the next procurement pressure point.