Silicon Is the Constraint: The SIA/Deloitte Numbers That Reframe Every Infrastructure Decision Through 2028

The Number That Changes the Analysis

Stop modeling AI infrastructure as a capital allocation problem. The SIA and Deloitte settled that debate on June 1, 2026, when they published "Powering AI: The Semiconductor Ecosystem at the Foundation of Data Centers." To meet global demand for new AI applications, government and industry will invest over $4 trillion in new data center infrastructure through 2028, of which up to $2.8 trillion will be spent on semiconductors. That is 70 cents of every dollar going to chips. The constraint is not balance sheets. It is fabs.

Chips account for more than 95% of a leading AI server rack's content value and more than 50% of the total capital expenditures required for building and operating an AI data center. The steel, concrete, cooling, power distribution, and network cabling that operators have traditionally treated as major capital items are statistical noise beside the silicon.

What the Teardown Actually Found

The SIA/Deloitte methodology matters before you act on the conclusions. The report conducted a virtual teardown of a state-of-the-art AI data server rack, the foundational unit of centralized AI infrastructure. This is a bill-of-materials analysis. It prices each component category and rolls them up.

A single AI server rack contains over 4,500 packaged chips, including advanced logic chips such as AI accelerators, ASICs, FPGAs, CPUs, data processing units, and networking chips. Compute trays alone account for approximately 4,000 chips per rack and represent between $1.5 million and $3.5 million in value. Power trays contain around 600 chips and contribute between $50,000 and $290,000 per rack, while network and management trays include roughly 100 chips valued at $17,000 to $25,000.

High-bandwidth memory, critical for AI training and inference, adds an estimated $400,000 to $600,000 per rack. HBM alone can exceed the cost of the entire non-semiconductor infrastructure. This data point should end internal debates about whether cooling or power deserves cost-reduction focus. It does not. Chip yield and allocation do.

The report also flags what the accelerator headlines obscure. While AI accelerators often receive the most attention, the supporting memory, power, and connectivity components are equally critical to overall system performance. AI requires the full range of semiconductor technologies, including logic, memory, and analog and foundational chips. Procurement bottlenecks anywhere in that stack delay rack deployments—not just GPU shortages.

The Growth Trajectory and What Drives It

The AI data center market is projected at an 88.8% CAGR from 2022 to 2028. But the pace slows to 56.3% from 2025 through 2028. The distinction matters. The first wave was a demand shock. The second is structural. Inference workloads are scaling alongside training. Each new model deployment extends rather than replaces prior chip demand.

Annual revenue for semiconductors used in AI data centers could reach $1.2 trillion by 2028, nearly tenfold growth over four years and exceeding total global semiconductor sales from 2025 across all end uses by more than 50%. The AI data center semiconductor market alone would outpace the entire current global chip market within two years. The industry is not cycling; it is restructuring.

The global semiconductor industry is expected to reach $975 billion in annual sales in 2026, a historic peak fueled by an intensifying AI infrastructure boom, with growth reaching 22% in 2025 and projected to accelerate to 26% in 2026.

The Supply Side Does Not Move That Fast

Hyperscalers can raise capital in days. TSMC cannot add leading-edge capacity in days, months, or even a single year. Advanced packaging, CoWoS interposers, and HBM stacking require years of tooling and qualification. TSMC CEO C.C. Wei said AI-related chip demand remains strong, with the company working to expand capacity and avoid becoming a bottleneck in the semiconductor supply chain. That statement hints at what TSMC is already thinking: it may be the bottleneck.

A leading AI chip manufacturer has secured about 800,000 wafers for its main chip in 2026 and produces about 20 chips per wafer, suggesting approximately 16 million chips in total. That allocation ceiling locks in well before the fiscal year starts. Operators without 2025 planning cycle allocations do not get 2026 chips. They wait.

This explains why foundry relationships have become a structural moat equivalent to fiber routes or power purchase agreements. NVIDIA's position is not purely about GPU architecture. It is about accumulated TSMC allocation priority. Custom silicon programs at hyperscalers—Google's TPUs, Amazon's Trainium and Inferentia, Microsoft's Maia—are not cost optimization plays. They are supply-chain hedges. Each proprietary wafer is one that does not sit in an allocation queue.

High-value AI chips now drive roughly half of total revenue but represent less than 0.2% of total unit volume. Extreme value concentration at the leading edge makes allocation power decisive. One delayed accelerator shipment can stall an entire data center.

Implications for Operators and Investors

The 95% rack-value figure has direct consequences for ROI calculation. Marginal improvements in chip efficiency or yield compound faster than any other infrastructure variable. A 10% improvement in accelerator performance-per-watt reshapes power and cooling requirements, rack density economics, and the effective cost of compute. Operators should track TSMC and Samsung wafer utilization with the same rigor they apply to power purchase agreements.

For hyperscaler bond investors, the risk has shifted. Revenue visibility now depends on chip allocation certainty, not demand. These companies can sell every GPU-hour they can deploy. The chips are already ordered and backlogs are full; data centers are under construction. The next 12 months look solid. But 2027 and 2028 could diverge sharply from current expectations. The downside is not demand collapse. It is a fab delay.

Tier-2 and Tier-3 cloud providers without direct foundry relationships face a disadvantage that will not self-correct. They cannot outbid hyperscalers for leading-edge allocation. Their options are differentiation on workload type, geography, or model size—areas where older architectures still work—or consolidation.

What to Watch, in Order

1. Fab delay signals at TSMC Arizona and Samsung Taylor. Any slip in CoWoS or advanced packaging capacity is a direct earnings headwind for hyperscalers with 2027 commitments. Watch quarterly calls for language around "capacity timing" rather than demand.

2. HBM pricing in 2027 contract negotiations. HBM contract prices are expected to rise sharply in 2027 as tight DRAM supply gives memory suppliers greater pricing power. The GPU gets attention; the HBM limits the rack.

3. Custom silicon program announcements. Every hyperscaler ASIC program is a supply-chain diversification move. Cadence and volume commitments from hyperscalers to TSMC for proprietary designs signal how seriously each company treats allocation risk.

4. Export control evolution. The Trump administration's Pax Silica Initiative and AI Exports Program will shape which geographies access advanced chips. Geographic bifurcation is not future risk; it is current reality. Watch for tightening or loosening of H20-class restrictions, which directly affects tier-2 providers in non-allied markets.

5. Consolidation among smaller cloud providers. Companies that cannot secure leading-edge allocations will face margin compression and acquisition pressure from operators with foundry access. The first significant deal in this cohort will signal that supply constraint has become a market structure event.